//]]>

Power-Aware Testing and Test Strategies for Low Power Devices (Record no. 10120)

000 -LEADER
fixed length control field 03388nam a22004215i 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20140310143331.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 110414s2010 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781441909282
978-1-4419-0928-2
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
264 #1 -
-- Boston, MA :
-- Springer US,
-- 2010.
912 ## -
-- ZDB-2-ENG
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Girard, Patrick.
Relator term editor.
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE
Title Power-Aware Testing and Test Strategies for Low Power Devices
Medium [electronic resource] /
Statement of responsibility, etc edited by Patrick Girard, Nicola Nicolici, Xiaoqing Wen.
300 ## - PHYSICAL DESCRIPTION
Extent XXII, 353p. 444 illus., 222 illus. in color.
Other physical details online resource.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Fundamentals of VLSI Testing -- Power Issues During Test -- Low-Power Test Pattern Generation -- Power-Aware Design-for-Test -- Power-Aware Test Data Compression and BIST -- Power-Aware System-Level Test Planning -- Low-Power Design Techniques and Test Implications -- Test Strategies for Multivoltage Designs -- Test Strategies for Gated Clock Designs -- Test of Power Management Structures -- EDA Solution for Power-Aware Design-for-Test.
520 ## - SUMMARY, ETC.
Summary, etc Power-Aware Testing and Test Strategies for Low-Power Devices Edited by: Patrick Girard, Research Director, CNRS / LIRMM, France Nicola Nicolici, Associate Professor, McMaster University, Canada Xiaoqing Wen, Professor, Kyushu Institute of Technology, Japan Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and Electronic Design Automation (EDA) solutions for testing low-power devices. The first comprehensive book on power-aware test for (low-power) circuits and systems Shows readers how low-power devices can be tested safely without affecting yield and reliability Includes necessary background information on design-for-test and low-power design Covers in detail power-constrained test techniques, including power-aware automatic test pattern generation, design-for-test, built-in self-test and test compression Presents state-of-the-art industrial practices and EDA solutions
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Computer aided design.
Topical term or geographic name as entry element Systems engineering.
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Circuits and Systems.
Topical term or geographic name as entry element Computer-Aided Engineering (CAD, CAE) and Design.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Nicolici, Nicola.
Relator term editor.
Personal name Wen, Xiaoqing.
Relator term editor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9781441909275
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-1-4419-0928-2
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Item type E-Book
Copies
Price effective from Permanent location Date last seen Not for loan Date acquired Source of classification or shelving scheme Koha item type Damaged status Lost status Withdrawn status Current location Full call number
2014-03-27AUM Main Library2014-03-27 2014-03-27 E-Book   AUM Main Library621.3815