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20140310143331.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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100316s2010 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781441909442 |
|
978-1-4419-0944-2 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815 |
| Edition number |
23 |
| 264 #1 - |
|---|
| -- |
Boston, MA : |
| -- |
Springer US, |
| -- |
2010. |
| 912 ## - |
|---|
| -- |
ZDB-2-ENG |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Gulati, Kanupriya. |
| Relator term |
author. |
| 245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
|---|
| Title |
Hardware Acceleration of EDA Algorithms |
| Medium |
[electronic resource] : |
| Remainder of title |
Custom ICs, FPGAs and GPUs / |
| Statement of responsibility, etc |
by Kanupriya Gulati, Sunil P. Khatri. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
X, 194p. 65 illus. |
| Other physical details |
online resource. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Alternative Hardware Platforms -- Hardware Platforms -- GPU Architecture and the CUDA Programming Model -- Control Dominated Category -- Accelerating Boolean Satisfiability on a Custom IC -- Accelerating Boolean Satisfiability on an FPGA -- Accelerating Boolean Satisfiability on a Graphics Processing Unit -- Control Plus Data Parallel Applications -- Accelerating statistical static Timing Analysis Using Graphics Processors -- Accelerating Fault Simulation Using Graphics Processors -- Fault Table Generation Using Graphics Processors -- Accelerating Circuit Simulation Using Graphics Processors -- Automated Generation of GPU Code -- Automated Approach for Graphics Processor Based Software Acceleration -- Conclusions. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs Kanupriya Gulati Sunil P. Khatri This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms. This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition. In particular, this book: Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms; Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X; Helps the reader by presenting example algorithms which may be used by the reader to determine how best to accelerate their specific EDA algorithm; Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints; Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Engineering. |
|
|---|
| Topical term or geographic name as entry element |
Computer aided design. |
|
|---|
| Topical term or geographic name as entry element |
Systems engineering. |
|
|---|
| Topical term or geographic name as entry element |
Engineering. |
|
|---|
| Topical term or geographic name as entry element |
Circuits and Systems. |
|
|---|
| Topical term or geographic name as entry element |
Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Khatri, Sunil P. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Printed edition: |
| International Standard Book Number |
9781441909435 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-1-4419-0944-2 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Item type |
E-Book |
