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Minimizing and Exploiting Leakage in VLSI Design (Record no. 10126)

000 -LEADER
fixed length control field 04800nam a22004455i 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20140310143331.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100301s2010 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781441909503
978-1-4419-0950-3
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
264 #1 -
-- Boston, MA :
-- Springer US,
-- 2010.
912 ## -
-- ZDB-2-ENG
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Jayakumar, Nikhil.
Relator term author.
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE
Title Minimizing and Exploiting Leakage in VLSI Design
Medium [electronic resource] /
Statement of responsibility, etc by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri.
300 ## - PHYSICAL DESCRIPTION
Other physical details online resource.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results.
520 ## - SUMMARY, ETC.
Summary, etc Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Computer aided design.
Topical term or geographic name as entry element Systems engineering.
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Circuits and Systems.
Topical term or geographic name as entry element Computer-Aided Engineering (CAD, CAE) and Design.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Paul, Suganth.
Relator term author.
Personal name Garg, Rajesh.
Relator term author.
Personal name Gulati, Kanupriya.
Relator term author.
Personal name Khatri, Sunil P.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9781441909497
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-1-4419-0950-3
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Item type E-Book
Copies
Price effective from Permanent location Date last seen Not for loan Date acquired Source of classification or shelving scheme Koha item type Damaged status Lost status Withdrawn status Current location Full call number
2014-03-27AUM Main Library2014-03-27 2014-03-27 E-Book   AUM Main Library621.3815
Languages: 
English |
العربية