000 -LEADER |
fixed length control field |
02875nam a22004215i 4500 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
OSt |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20140310143332.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr nn 008mamaa |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
100927s2011 xxu| s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781441969118 |
|
978-1-4419-6911-8 |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
23 |
264 #1 - |
-- |
Boston, MA : |
-- |
Springer US : |
-- |
Imprint: Springer, |
-- |
2011. |
912 ## - |
-- |
ZDB-2-ENG |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Silvano, Cristina. |
Relator term |
editor. |
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
Title |
Low Power Networks-on-Chip |
Medium |
[electronic resource] / |
Statement of responsibility, etc |
edited by Cristina Silvano, Marcello Lajolo, Gianluca Palermo. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
X, 300p. 100 illus. |
Other physical details |
online resource. |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
Network-on-Chip Power Estimation -- Timing -- synchronous/asynchronous communication -- Network-on-Chip link design -- Topology exploration -- Network-on-Chip support for CMP/MPSoCs -- Network design for 3D stacked logic and memory -- Beyond the wired Network-on-Chip. |
520 ## - SUMMARY, ETC. |
Summary, etc |
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. •Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; •Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; •Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Engineering. |
|
Topical term or geographic name as entry element |
Computer aided design. |
|
Topical term or geographic name as entry element |
Systems engineering. |
|
Topical term or geographic name as entry element |
Engineering. |
|
Topical term or geographic name as entry element |
Circuits and Systems. |
|
Topical term or geographic name as entry element |
Computer-Aided Engineering (CAD, CAE) and Design. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Lajolo, Marcello. |
Relator term |
editor. |
|
Personal name |
Palermo, Gianluca. |
Relator term |
editor. |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Display text |
Printed edition: |
International Standard Book Number |
9781441969101 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-1-4419-6911-8 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
|
Item type |
E-Book |