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| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20140310143332.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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101110s2011 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781441974181 |
|
978-1-4419-7418-1 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815 |
| Edition number |
23 |
| 264 #1 - |
|---|
| -- |
Boston, MA : |
| -- |
Springer US, |
| -- |
2011. |
| 912 ## - |
|---|
| -- |
ZDB-2-ENG |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Bhunia, Swarup. |
| Relator term |
editor. |
| 245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
|---|
| Title |
Low-Power Variation-Tolerant Design in Nanometer Silicon |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc |
edited by Swarup Bhunia, Saibal Mukhopadhyay. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
1. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
X, 240p. 100 illus. |
| Other physical details |
online resource. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction and Motivation -- Background on Power Dissipation -- Background on Parameter Variations -- Low power Logic Design under Variations -- Low Power Memory Design under Variations -- System and Architecture Level Design -- Emerging Challenges and Solution Approach -- Conclusion and Discussion. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. Coverage includes logic and memory design, modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. •Introduces readers to some of the most important challenges in low-power and variation-tolerant IC design in nanoscale technologies; •Presents a holistic view of Low-Power Variation-Tolerant Design, at different levels of design abstraction, starting from device to circuit, architecture and system; •Offers comprehensive coverage of modeling, analysis and design methodology for low power and variation-tolerant logic circuits, memory and systems, micro-architecture, DSP, mixed-signal and FPGAs, including current industrial practices, technology scaling trends, and emerging challenges; •Describes in detail modeling and analysis of different variation effects (die-to-die and within-die, process and temporal) on low-power designs; Includes coverage of ultra low-power and robust sub-threshold design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Engineering. |
|
|---|
| Topical term or geographic name as entry element |
Computer aided design. |
|
|---|
| Topical term or geographic name as entry element |
Systems engineering. |
|
|---|
| Topical term or geographic name as entry element |
Engineering. |
|
|---|
| Topical term or geographic name as entry element |
Circuits and Systems. |
|
|---|
| Topical term or geographic name as entry element |
Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Mukhopadhyay, Saibal. |
| Relator term |
editor. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Printed edition: |
| International Standard Book Number |
9781441974174 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-1-4419-7418-1 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Item type |
E-Book |
