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Robust SRAM Designs and Analysis (Record no. 10617)

000 -LEADER
fixed length control field 02713nam a22004335i 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20140310143336.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 120731s2013 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781461408185
978-1-4614-0818-5
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
264 #1 -
-- New York, NY :
-- Springer New York :
-- Imprint: Springer,
-- 2013.
912 ## -
-- ZDB-2-ENG
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Singh, Jawar.
Relator term author.
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE
Title Robust SRAM Designs and Analysis
Medium [electronic resource] /
Statement of responsibility, etc by Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan.
300 ## - PHYSICAL DESCRIPTION
Extent XI, 166 p. 167 illus.
Other physical details online resource.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Introduction to SRAM -- Design Metrics of SRAM Bitcell -- Single-ended SRAM Bitcell Design -- 2-Port SRAM Bitcell Design -- SRAM Bitcell Design Using Unidirectional Devices -- NBTI and its Effect on SRAM.
520 ## - SUMMARY, ETC.
Summary, etc This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Electronics.
Topical term or geographic name as entry element Systems engineering.
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Circuits and Systems.
Topical term or geographic name as entry element Electronics and Microelectronics, Instrumentation.
Topical term or geographic name as entry element Nanotechnology and Microengineering.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Mohanty, Saraju P.
Relator term author.
Personal name Pradhan, Dhiraj K.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9781461408178
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-1-4614-0818-5
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Item type E-Book
Copies
Price effective from Permanent location Date last seen Not for loan Date acquired Source of classification or shelving scheme Koha item type Damaged status Lost status Withdrawn status Current location Full call number
2014-03-29AUM Main Library2014-03-29 2014-03-29 E-Book   AUM Main Library621.3815
Languages: 
English |
العربية