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003 - CONTROL NUMBER IDENTIFIER |
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005 - DATE AND TIME OF LATEST TRANSACTION |
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20140310143337.0 |
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111201s2012 xxu| s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781461414278 |
|
978-1-4614-1427-8 |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
23 |
264 #1 - |
-- |
New York, NY : |
-- |
Springer New York, |
-- |
2012. |
912 ## - |
-- |
ZDB-2-ENG |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Kaźmierski, Tom J. |
Relator term |
editor. |
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
Title |
System Specification and Design Languages |
Medium |
[electronic resource] : |
Remainder of title |
Selected Contributions from FDL 2010 / |
Statement of responsibility, etc |
edited by Tom J. Kaźmierski, Adam Morawiec. |
250 ## - EDITION STATEMENT |
Edition statement |
1. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
XII, 256 p. |
Other physical details |
online resource. |
440 1# - SERIES STATEMENT/ADDED ENTRY--TITLE |
Title |
Lecture Notes in Electrical Engineering, |
International Standard Serial Number |
1876-1100 ; |
Volume number/sequential designation |
106 |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors -- Evaluating Debugging Algorithms from a Qualitative Perspective -- Mapping of Concurrent Object-oriented Models to Extend Real-time Task Networks -- SystemC-A Modelling of Mixed-technology Systems with Distributed Behaviour -- A Framework for Interactive Refinement of Mixed HW/SW/Analog Systems -- Bottom-up Verification for CMOS Photonic Linear Heterogeneous System -- Towards Abstract Analysis Techniques for Range Based System Simulations -- Modeling Time-triggered Architecture Based Real-time Systems Using SystemC -- Towards the Development of a Set of Transaction Level Models - A Feature-oriented Approach -- Rapid Prototyping of Complex HW/SW Systems Using a Timing and Power Aware ESL Framework -- Towards Accurate Source-level Annotation of Low-level Properties Obtained from Optimized Binary Code -- Architecture Specifications in CλaSH -- SyReC: A Programming Language for Synthesis of Reversible Circuits -- Logical Time @ Work: Capturing Data Dependencies and Platform Constraints -- Formal Support for Untimed MARTE-SystemC Interoperability. |
520 ## - SUMMARY, ETC. |
Summary, etc |
This book brings together a selection of the best papers from the thirteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in Southampton, UK in September 2010. FDL is a well established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modelling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. Covers design verification, automatic synthesis and mechanized debug aids; Includes language-based modeling and design techniques for embedded systems; Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains; Includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE). |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Engineering. |
|
Topical term or geographic name as entry element |
Computer science. |
|
Topical term or geographic name as entry element |
Electronics. |
|
Topical term or geographic name as entry element |
Systems engineering. |
|
Topical term or geographic name as entry element |
Engineering. |
|
Topical term or geographic name as entry element |
Circuits and Systems. |
|
Topical term or geographic name as entry element |
Electronics and Microelectronics, Instrumentation. |
|
Topical term or geographic name as entry element |
Processor Architectures. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Morawiec, Adam. |
Relator term |
editor. |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Display text |
Printed edition: |
International Standard Book Number |
9781461414261 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-1-4614-1427-8 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
|
Item type |
E-Book |