000 -LEADER |
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02919nam a22004455i 4500 |
003 - CONTROL NUMBER IDENTIFIER |
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005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20140310143358.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr nn 008mamaa |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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101029s2011 ne | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9789048193981 |
|
978-90-481-9398-1 |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
23 |
264 #1 - |
-- |
Dordrecht : |
-- |
Springer Netherlands, |
-- |
2011. |
912 ## - |
-- |
ZDB-2-ENG |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Fan, Yongquan. |
Relator term |
author. |
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
Title |
Accelerating Test, Validation and Debug of High Speed Serial Interfaces |
Medium |
[electronic resource] / |
Statement of responsibility, etc |
by Yongquan Fan, Zeljko Zilic. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
XII, 250p. 120 illus., 60 illus. in color. |
Other physical details |
online resource. |
520 ## - SUMMARY, ETC. |
Summary, etc |
High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces. Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Engineering. |
|
Topical term or geographic name as entry element |
Computer system performance. |
|
Topical term or geographic name as entry element |
Software engineering. |
|
Topical term or geographic name as entry element |
Electronics. |
|
Topical term or geographic name as entry element |
Systems engineering. |
|
Topical term or geographic name as entry element |
Engineering. |
|
Topical term or geographic name as entry element |
Circuits and Systems. |
|
Topical term or geographic name as entry element |
Software Engineering/Programming and Operating Systems. |
|
Topical term or geographic name as entry element |
Electronics and Microelectronics, Instrumentation. |
|
Topical term or geographic name as entry element |
System Performance and Evaluation. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Zilic, Zeljko. |
Relator term |
author. |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Display text |
Printed edition: |
International Standard Book Number |
9789048193974 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-90-481-9398-1 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
|
Item type |
E-Book |