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20140310143358.0 |
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120921s2013 ne | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9789048196449 |
|
978-90-481-9644-9 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815 |
| Edition number |
23 |
| 264 #1 - |
|---|
| -- |
Dordrecht : |
| -- |
Springer Netherlands : |
| -- |
Imprint: Springer, |
| -- |
2013. |
| 912 ## - |
|---|
| -- |
ZDB-2-ENG |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Krishnaswamy, Smita. |
| Relator term |
author. |
| 245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
|---|
| Title |
Design, Analysis and Test of Logic Circuits Under Uncertainty |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc |
by Smita Krishnaswamy, Igor L. Markov, John P. Hayes. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
XI, 123 p. 71 illus. |
| Other physical details |
online resource. |
| 440 1# - SERIES STATEMENT/ADDED ENTRY--TITLE |
|---|
| Title |
Lecture Notes in Electrical Engineering, |
| International Standard Serial Number |
1876-1100 ; |
| Volume number/sequential designation |
115 |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction -- Probabilistic Transfer Matrices -- Computing with Probabilistic Transfer Matrices -- Testing Logic Circuits for Probabilistic Faults -- Signtaure-based Reliability Analysis -- Design for Robustness -- Summary and Extensions. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits. To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits. The book describes techniques for: • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework; • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations; • Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance; • Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Engineering. |
|
|---|
| Topical term or geographic name as entry element |
Computer hardware. |
|
|---|
| Topical term or geographic name as entry element |
Computer science. |
|
|---|
| Topical term or geographic name as entry element |
Logic design. |
|
|---|
| Topical term or geographic name as entry element |
Operating systems (Computers). |
|
|---|
| Topical term or geographic name as entry element |
Algebra |
| General subdivision |
Data processing. |
|
|---|
| Topical term or geographic name as entry element |
Systems engineering. |
|
|---|
| Topical term or geographic name as entry element |
Engineering. |
|
|---|
| Topical term or geographic name as entry element |
Circuits and Systems. |
|
|---|
| Topical term or geographic name as entry element |
Arithmetic and Logic Structures. |
|
|---|
| Topical term or geographic name as entry element |
Computer Hardware. |
|
|---|
| Topical term or geographic name as entry element |
Performance and Reliability. |
|
|---|
| Topical term or geographic name as entry element |
Logic Design. |
|
|---|
| Topical term or geographic name as entry element |
Symbolic and Algebraic Manipulation. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Markov, Igor L. |
| Relator term |
author. |
|
|---|
| Personal name |
Hayes, John P. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
|---|
| Display text |
Printed edition: |
| International Standard Book Number |
9789048196432 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-90-481-9644-9 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Item type |
E-Book |
