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005 - DATE AND TIME OF LATEST TRANSACTION |
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20140310144050.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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100709s2010 gw | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9783642142956 |
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978-3-642-14295-6 |
050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
Classification number |
QA76.9.L63 |
|
Classification number |
QA76.5913 |
|
Classification number |
QA76.63 |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
005.1015113 |
Edition number |
23 |
264 #1 - |
-- |
Berlin, Heidelberg : |
-- |
Springer Berlin Heidelberg, |
-- |
2010. |
912 ## - |
-- |
ZDB-2-SCS |
|
-- |
ZDB-2-LNC |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Touili, Tayssir. |
Relator term |
editor. |
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
Title |
Computer Aided Verification |
Medium |
[electronic resource] : |
Remainder of title |
22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010. Proceedings / |
Statement of responsibility, etc |
edited by Tayssir Touili, Byron Cook, Paul Jackson. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
XVI, 676p. 169 illus. |
Other physical details |
online resource. |
440 1# - SERIES STATEMENT/ADDED ENTRY--TITLE |
Title |
Lecture Notes in Computer Science, |
International Standard Serial Number |
0302-9743 ; |
Volume number/sequential designation |
6174 |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
Invited Talks -- Policy Monitoring in First-Order Temporal Logic -- Retrofitting Legacy Code for Security -- Quantitative Information Flow: From Theory to Practice? -- Memory Management in Concurrent Algorithms -- Invited Tutorials -- ABC: An Academic Industrial-Strength Verification Tool -- There’s Plenty of Room at the Bottom: Analyzing and Verifying Machine Code -- Constraint Solving for Program Verification: Theory and Practice by Example -- Session 1. Software Model Checking -- Invariant Synthesis for Programs Manipulating Lists with Unbounded Data -- Termination Analysis with Compositional Transition Invariants -- Lazy Annotation for Program Testing and Verification -- The Static Driver Verifier Research Platform -- Dsolve: Safety Verification via Liquid Types -- Contessa: Concurrency Testing Augmented with Symbolic Analysis -- Session 2. Model Checking and Automata -- Simulation Subsumption in Ramsey-Based Büchi Automata Universality and Inclusion Testing -- Efficient Emptiness Check for Timed Büchi Automata -- Session 3. Tools -- Merit: An Interpolating Model-Checker -- Breach, A Toolbox for Verification and Parameter Synthesis of Hybrid Systems -- Jtlv: A Framework for Developing Verification Algorithms -- Petruchio: From Dynamic Networks to Nets -- Session 4. Counter and Hybrid Systems Verification -- Synthesis of Quantized Feedback Control Software for Discrete Time Linear Hybrid Systems -- Safety Verification for Probabilistic Hybrid Systems -- A Logical Product Approach to Zonotope Intersection -- Fast Acceleration of Ultimately Periodic Relations -- An Abstraction-Refinement Approach to Verification of Artificial Neural Networks -- Session 5. Memory Consistency -- Fences in Weak Memory Models -- Generating Litmus Tests for Contrasting Memory Consistency Models -- Session 6. Verification of Hardware and Low Level Code -- Directed Proof Generation for Machine Code -- Verifying Low-Level Implementations of High-Level Datatypes -- Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics -- Efficient Reachability Analysis of Büchi Pushdown Systems for Hardware/Software Co-verification -- Session 7. Tools -- LTSmin: Distributed and Symbolic Reachability -- libalf: The Automata Learning Framework -- Session 8. Synthesis -- Symbolic Bounded Synthesis -- Measuring and Synthesizing Systems in Probabilistic Environments -- Achieving Distributed Control through Model Checking -- Robustness in the Presence of Liveness -- RATSY – A New Requirements Analysis Tool with Synthesis -- Comfusy: A Tool for Complete Functional Synthesis -- Session 9. Concurrent Program Verification I -- Universal Causality Graphs: A Precise Happens-Before Model for Detecting Bugs in Concurrent Programs -- Automatically Proving Linearizability -- Model Checking of Linearizability of Concurrent List Implementations -- Local Verification of Global Invariants in Concurrent Programs -- Abstract Analysis of Symbolic Executions -- Session 10. Compositional Reasoning -- Automated Assume-Guarantee Reasoning through Implicit Learning -- Learning Component Interfaces with May and Must Abstractions -- A Dash of Fairness for Compositional Reasoning -- SPLIT: A Compositional LTL Verifier -- Session 11. Tools -- A Model Checker for AADL -- PESSOA: A Tool for Embedded Controller Synthesis -- Session 12. Decision Procedures -- On Array Theory of Bounded Elements -- Quantifier Elimination by Lazy Model Enumeration -- Session 13. Concurrent Program Verification II -- Bounded Underapproximations -- Global Reachability in Bounded Phase Multi-stack Pushdown Systems -- Model-Checking Parameterized Concurrent Programs Using Linear Interfaces -- Dynamic Cutoff Detection in Parameterized Concurrent Programs -- Session 14. Tools -- PARAM: A Model Checker for Parametric Markov Models -- Gist: A Solver for Probabilistic Games -- A NuSMV Extension for Graded-CTL Model Checking. |
520 ## - SUMMARY, ETC. |
Summary, etc |
This book constitutes the refereed proceedings of the 22nd International Conference on Computer Aided Verification, CAV 2010, held in Edinburgh, UK, in July 2010 as part of the Federated Logic Conference, FLoC 2010. The 34 revised full papers presented together with 17 tool papers, 4 invited talks and 3 invited tutorials were carefully reviewed and selected from 101 regular paper and 44 tool paper submissions. The papers are dedicated to the advancement of the theory and practice of computer-assisted formal analysis methods for hardware and software systems. They are organized in topical sections on software model checking; model checking and automata; tools; counter and hybrid systems verification; memory consistency; verification of hardware and low level code; synthesis; concurrent program verification; compositional reasoning; and decision procedures. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Computer science. |
|
Topical term or geographic name as entry element |
Computer Communication Networks. |
|
Topical term or geographic name as entry element |
Software engineering. |
|
Topical term or geographic name as entry element |
Logic design. |
|
Topical term or geographic name as entry element |
Artificial intelligence. |
|
Topical term or geographic name as entry element |
Computer Science. |
|
Topical term or geographic name as entry element |
Logics and Meanings of Programs. |
|
Topical term or geographic name as entry element |
Software Engineering. |
|
Topical term or geographic name as entry element |
Programming Languages, Compilers, Interpreters. |
|
Topical term or geographic name as entry element |
Mathematical Logic and Formal Languages. |
|
Topical term or geographic name as entry element |
Artificial Intelligence (incl. Robotics). |
|
Topical term or geographic name as entry element |
Computer Communication Networks. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Cook, Byron. |
Relator term |
editor. |
|
Personal name |
Jackson, Paul. |
Relator term |
editor. |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Display text |
Printed edition: |
International Standard Book Number |
9783642142949 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-3-642-14295-6 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
|
Item type |
E-Book |