| 000 -LEADER |
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| fixed length control field |
04021nam a22003975i 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20140310151132.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
120301s2010 fr | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9789491216336 |
|
978-94-91216-33-6 |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7895.M4 |
|
|---|
| Classification number |
TK7895.M4 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
004.53 |
| Edition number |
23 |
| 264 #1 - |
|---|
| -- |
Paris : |
| -- |
Atlantis Press, |
| -- |
2010. |
| 912 ## - |
|---|
| -- |
ZDB-2-SCS |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Abdallah, Abderazek Ben. |
| Relator term |
author. |
| 245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
|---|
| Title |
Multicore Systems On-Chip: Practical Software/Hardware Design |
| Medium |
[electronic resource] / |
| Statement of responsibility, etc |
by Abderazek Ben Abdallah. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
XVIII, 180p. |
| Other physical details |
online resource. |
| 440 1# - SERIES STATEMENT/ADDED ENTRY--TITLE |
|---|
| Title |
Atlantis Ambient and Pervasive Intelligence, |
| International Standard Serial Number |
1875-7669 ; |
| Volume number/sequential designation |
3 |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Multicore Systems Design Methodology -- Design for Low Power Systems -- Network-on-Chip for Multi- and Many-Core Systems -- Parallelizing Compiler for High Performance Computing -- Dual-Execution Processor Architecture for Embedded Computing -- Low Power Embedded Core Architecture -- ReconfigurableMulticore Architectures. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
Conventional on-chip communication design mostly use ad-hoc approaches that fail to meet the challenges posed by the next-generation MultiCore Systems on-chip (MCSoC) designs. These major challenges include wiring delay, predictability, diverse interconnection architectures, and power dissipation. A Network-on-Chip (NoC) paradigm is emerging as the solution for the problems of interconnecting dozens of cores into a single system on-chip. However, there are many problems associated with the design of such systems. These problems arise from non-scalable global wire delays, failure to achieve global synchronization, and difficulties associated with non-scalable bus-based functional interconnects. The book consists of three parts, with each part being subdivided into four chapters. The first part deals with design and methodology issues. The architectures used in conventional methods of MCSoCs design and custom multiprocessor architectures are not flexible enough to meet the requirements of different application domains and not scalable enough to meet different computation needs and different complexities of various applications. Several chapters of the first part will emphasize on the design techniques and methodologies. The second part covers the most critical part of MCSoCs design — the interconnections. One approach to addressing the design methodologies is to adopt the so-called reusability feature to boost design productivity. In the past years, the primitive design units evolved from transistors to gates, finite state machines, and processor cores. The network-on-chip paradigm offers this attractive property for the future and will be able to close the productivity gap. The last part of this book delves into MCSoCs validations and optimizations. A more qualitative approach of system validation is based on the use of formal techniques for hardware design. The main advantage of formal methods is the possibility to prove the validity of essential design requirements. As formal languages have a mathematical foundation, it is possible to formally extract and verify these desired properties of the complete abstract state space. Online testing techniques for identifying faults that can lead to system failure are also surveyed. Emphasis is given to analytical redundancy-based techniques that have been developed for fault detection and isolation in the automatic control area. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Computer science. |
|
|---|
| Topical term or geographic name as entry element |
Memory management (Computer science). |
|
|---|
| Topical term or geographic name as entry element |
Computer Science. |
|
|---|
| Topical term or geographic name as entry element |
Memory Structures. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
|---|
| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
|---|
| Title |
Springer eBooks |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
http://dx.doi.org/10.2991/978-94-91216-33-6 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Item type |
E-Book |
