Multicore Systems On-Chip: Practical Software/Hardware Design (Record no. 22558)

000 -LEADER
fixed length control field 04008nam a22004215i 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20140310151132.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 130720s2013 fr | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9789491216923
978-94-91216-92-3
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA75.5-76.95
Classification number TK7885-7895
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004
Edition number 23
264 #1 -
-- Paris :
-- Atlantis Press :
-- Imprint: Atlantis Press,
-- 2013.
912 ## -
-- ZDB-2-SCS
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Ben Abdallah, Abderazek.
Relator term author.
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE
Title Multicore Systems On-Chip: Practical Software/Hardware Design
Medium [electronic resource] :
Remainder of title 2nd Edition /
Statement of responsibility, etc by Abderazek Ben Abdallah.
300 ## - PHYSICAL DESCRIPTION
Extent XXVI, 273 p. 196 illus., 79 illus. in color.
Other physical details online resource.
440 1# - SERIES STATEMENT/ADDED ENTRY--TITLE
Title Atlantis Ambient and Pervasive Intelligence,
International Standard Serial Number 1875-7669 ;
Volume number/sequential designation 7
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Introduction to Multicore Systems On-Chip -- Multicore SoCs Design Methods -- Multicore SoC Organization -- 2D Network-on-Chip -- 3D Network-on-Chip -- Network Interface Architecture and Design for 2D/3D NoCs -- Parallelizing Compiler for Single and Multicore Computing -- Power Optimization Techniques for Multicore SoCs -- Soft-Core Processor for Low-Power Embedded -- Dual-Execution Processor Architecture for Embedded -- Case Study: Deign of Embedded Multicore SoC.
520 ## - SUMMARY, ETC.
Summary, etc System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing. The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running. As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility. Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device’s functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip. Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processing cores and that load balancing between processing cores – especially heterogeneous cores – is very difficult.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer science.
Topical term or geographic name as entry element Computer hardware.
Topical term or geographic name as entry element Computer Science.
Topical term or geographic name as entry element Computer Hardware.
Topical term or geographic name as entry element Processor Architectures.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9789491216916
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.2991/978-94-91216-92-3
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Item type E-Book
Copies
Price effective from Permanent location Date last seen Not for loan Date acquired Source of classification or shelving scheme Koha item type Damaged status Lost status Withdrawn status Current location Full call number
2014-04-24AUM Main Library2014-04-24 2014-04-24 E-Book   AUM Main Library004