000 -LEADER |
fixed length control field |
00793cam a2200229 a 4500 |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20190530130931.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
091112s2011 maua b 001 0 eng |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9780136019282 (alk. paper) |
|
International Standard Book Number |
0136019285 (alk. paper) |
041 ## - Language |
Language code of text/sound track or separate title |
eng |
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.395 |
Edition number |
22 |
Item number |
C548 |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Ciletti, Michael D. |
9 (RLIN) |
225 |
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
Title |
Advanced digital design with the Verilog HDL / |
Statement of responsibility, etc |
Michael D. Ciletti. |
250 ## - EDITION STATEMENT |
Edition statement |
2nd ed. |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
Place of publication, distribution, etc |
Boston, MA : |
Name of publisher, distributor, etc |
Prentice Hall, |
Date of publication, distribution, etc |
2011. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
xviii, 965 p. : |
Other physical details |
ill. ; |
Dimensions |
24 cm. |
440 #0 - SERIES STATEMENT/ADDED ENTRY--TITLE |
Title |
Prentice Hall Xilinx design series |
9 (RLIN) |
18101 |
504 ## - BIBLIOGRAPHY, ETC. NOTE |
Bibliography, etc |
Includes bibliographical references and indexes. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Logic design |
General subdivision |
Data processing. |
9 (RLIN) |
226 |
|
Topical term or geographic name as entry element |
Verilog (Computer hardware description language) |
9 (RLIN) |
227 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
|
Item type |
Book |