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The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits (Record no. 9970)

000 -LEADER
fixed length control field 02704nam a22004215i 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20140310143330.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100301s2010 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780387471013
978-0-387-47101-3
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
264 #1 -
-- Boston, MA :
-- Springer US,
-- 2010.
912 ## -
-- ZDB-2-ENG
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Jespers, Paul.
Relator term author.
245 14 - IMMEDIATE SOURCE OF ACQUISITION NOTE
Title The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits
Medium [electronic resource] :
Remainder of title The semi-empirical and compact model approaches /
Statement of responsibility, etc by Paul Jespers.
300 ## - PHYSICAL DESCRIPTION
Extent XVI, 171p.
Other physical details online resource.
440 1# - SERIES STATEMENT/ADDED ENTRY--TITLE
Title Analog Circuits and Signal Processing
520 ## - SUMMARY, ETC.
Summary, etc How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Computer science.
Topical term or geographic name as entry element Systems engineering.
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Circuits and Systems.
Topical term or geographic name as entry element Processor Architectures.
Topical term or geographic name as entry element Solid State Physics.
Topical term or geographic name as entry element Spectroscopy and Microscopy.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9780387471006
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-0-387-47101-3
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Item type E-Book
Copies
Price effective from Permanent location Date last seen Not for loan Date acquired Source of classification or shelving scheme Koha item type Damaged status Lost status Withdrawn status Current location Full call number
2014-03-27AUM Main Library2014-03-27 2014-03-27 E-Book   AUM Main Library621.3815

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