Fault Tolerant Nanocomputing -- Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics -- Fault-Tolerant Design for Nanowire-Based Programmable Logic Arrays -- Built-In Self-Test and Defect Tolerance for Molecular Electronics-Based NanoFabrics -- The Prospect and Challenges of CNFET Based Circuits: A Physical Insight -- Computing with Nanowires: A Self Assembled Neuromorphic Architecture -- Computational Opportunities and CAD for Nanotechnologies.

Although complementary metal-oxide semiconductor (CMOS) technology will continue dominating the digital electronic circuits for the next 10-15 years, a number of grand challenges have emerged as the transistor size scales down. The rising costs of semiconductor mask and fabrication pose economic barriers to lithography. The quantum effects and increasing leakage power begin setting physical limits on continuous CMOS feature size shrinking. The research advances of innovative nano-scale devices have created great opportunities to surpass the barriers faced by CMOS technology, which include nanowires, carbon nanotube transistors, programmable molecular switches, resonant tunneling diodes, quantum dots, etc. However, the success of many nanotechnologies relies on the self-assembly fabrication process to fabricate circuits. The stochastic self-assembly fabrication, unfortunately, has low reliability with defect densities several orders of magnitude higher than conventional CMOS technology. Robust Nano-Computing focuses on various issues of robust nano-computing, defect-tolerance design for nano-technology at different design abstraction levels. It addresses both redundancy- and configuration-based methods as well as fault detecting techniques through the development of accurate computation models and tools. The contents present an insightful view of the ongoing researches on nano-electronic devices, circuits, architectures, and design methods, as well as provide promising directions for future research.