Library of American University of Madaba
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Nicopoulos, Chrysostomos.
Network-on-Chip Architectures A Holistic Design Exploration / [electronic resource] : by Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das. - XXII, 223p. online resource. - Lecture Notes in Electrical Engineering, 45 1876-1100 ; .
MICRO-Architectural Exploration -- A Baseline NoC Architecture -- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39] -- RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40] -- Exploring FaultoTolerant Network-on-Chip Architectures [37] -- On the Effects of Process Variation in Network-on-Chip Architectures [45] -- MACRO-Architectural Exploration -- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15] -- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43] -- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44] -- Digest of Additional NoC MACRO-Architectural Research -- Conclusions and Future Work.
The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.
9789048130313
Engineering.
Computer science.
Systems engineering.
Engineering.
Circuits and Systems.
Processor Architectures.
621.3815
Network-on-Chip Architectures A Holistic Design Exploration / [electronic resource] : by Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das. - XXII, 223p. online resource. - Lecture Notes in Electrical Engineering, 45 1876-1100 ; .
MICRO-Architectural Exploration -- A Baseline NoC Architecture -- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39] -- RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40] -- Exploring FaultoTolerant Network-on-Chip Architectures [37] -- On the Effects of Process Variation in Network-on-Chip Architectures [45] -- MACRO-Architectural Exploration -- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15] -- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43] -- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44] -- Digest of Additional NoC MACRO-Architectural Research -- Conclusions and Future Work.
The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.
9789048130313
Engineering.
Computer science.
Systems engineering.
Engineering.
Circuits and Systems.
Processor Architectures.
621.3815