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Network-on-Chip Architectures (Record no. 12430)

000 -LEADER
fixed length control field 03891nam a22004335i 4500
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20140310143357.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 110414s2010 ne | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9789048130313
978-90-481-3031-3
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
264 #1 -
-- Dordrecht :
-- Springer Netherlands,
-- 2010.
912 ## -
-- ZDB-2-ENG
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Nicopoulos, Chrysostomos.
Relator term author.
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE
Title Network-on-Chip Architectures
Medium [electronic resource] :
Remainder of title A Holistic Design Exploration /
Statement of responsibility, etc by Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das.
300 ## - PHYSICAL DESCRIPTION
Extent XXII, 223p.
Other physical details online resource.
440 1# - SERIES STATEMENT/ADDED ENTRY--TITLE
Title Lecture Notes in Electrical Engineering,
International Standard Serial Number 1876-1100 ;
Volume number/sequential designation 45
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note MICRO-Architectural Exploration -- A Baseline NoC Architecture -- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39] -- RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40] -- Exploring FaultoTolerant Network-on-Chip Architectures [37] -- On the Effects of Process Variation in Network-on-Chip Architectures [45] -- MACRO-Architectural Exploration -- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15] -- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43] -- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44] -- Digest of Additional NoC MACRO-Architectural Research -- Conclusions and Future Work.
520 ## - SUMMARY, ETC.
Summary, etc The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Computer science.
Topical term or geographic name as entry element Systems engineering.
Topical term or geographic name as entry element Engineering.
Topical term or geographic name as entry element Circuits and Systems.
Topical term or geographic name as entry element Processor Architectures.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Narayanan, Vijaykrishnan.
Relator term author.
Personal name Das, Chita R.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9789048130306
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/978-90-481-3031-3
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Item type E-Book
Copies
Price effective from Permanent location Date last seen Not for loan Date acquired Source of classification or shelving scheme Koha item type Damaged status Lost status Withdrawn status Current location Full call number
2014-04-03AUM Main Library2014-04-03 2014-04-03 E-Book   AUM Main Library621.3815
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