000 -LEADER |
fixed length control field |
02844nam a22004215i 4500 |
003 - CONTROL NUMBER IDENTIFIER |
control field |
OSt |
005 - DATE AND TIME OF LATEST TRANSACTION |
control field |
20140310143357.0 |
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
fixed length control field |
cr nn 008mamaa |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
100301s2010 ne | s |||| 0|eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9789048134434 |
|
978-90-481-3443-4 |
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.3815 |
Edition number |
23 |
264 #1 - |
-- |
Dordrecht : |
-- |
Springer Netherlands, |
-- |
2010. |
912 ## - |
-- |
ZDB-2-ENG |
100 1# - MAIN ENTRY--PERSONAL NAME |
Personal name |
Hong, Dongwoo. |
Relator term |
author. |
245 10 - IMMEDIATE SOURCE OF ACQUISITION NOTE |
Title |
Efficient Test Methodologies for High-Speed Serial Links |
Medium |
[electronic resource] / |
Statement of responsibility, etc |
by Dongwoo Hong, Kwang-Ting Cheng. |
300 ## - PHYSICAL DESCRIPTION |
Extent |
XII, 98p. |
Other physical details |
online resource. |
440 1# - SERIES STATEMENT/ADDED ENTRY--TITLE |
Title |
Lecture Notes in Electrical Engineering, |
International Standard Serial Number |
1876-1100 ; |
Volume number/sequential designation |
51 |
505 0# - FORMATTED CONTENTS NOTE |
Formatted contents note |
An Efficient Jitter Measurement Technique -- BER Estimation for Linear Clock and Data Recovery Circuit -- BER Estimation for Non-linear Clock and Data Recovery Circuit -- Gaps in Timing Margining Test -- An Accurate Jitter Estimation Technique -- A Two-Tone Test Method for Continuous-Time Adaptive Equalizers -- Conclusions. |
520 ## - SUMMARY, ETC. |
Summary, etc |
With the increasing demand for higher data bandwidth, communication systems’ data rates have reached the multi-gigahertz range and even beyond. Advances in semiconductor technologies have accelerated the adoption of high-speed serial interfaces, such as PCI-Express, Serial-ATA, and XAUI, in order to mitigate the high pin-count and the data-channel skewing problems. However, with the increasing number of I/O pins and greater data rates, significant challenges arise for testing high-speed interfaces in terms of test cost and quality, especially in high volume manufacturing (HVM) environments. Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques. |
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Engineering. |
|
Topical term or geographic name as entry element |
Computer science. |
|
Topical term or geographic name as entry element |
Systems engineering. |
|
Topical term or geographic name as entry element |
Engineering. |
|
Topical term or geographic name as entry element |
Circuits and Systems. |
|
Topical term or geographic name as entry element |
Register-Transfer-Level Implementation. |
700 1# - ADDED ENTRY--PERSONAL NAME |
Personal name |
Cheng, Kwang-Ting. |
Relator term |
author. |
710 2# - ADDED ENTRY--CORPORATE NAME |
Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
773 0# - HOST ITEM ENTRY |
Title |
Springer eBooks |
776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
Display text |
Printed edition: |
International Standard Book Number |
9789048134427 |
856 40 - ELECTRONIC LOCATION AND ACCESS |
Uniform Resource Identifier |
http://dx.doi.org/10.1007/978-90-481-3443-4 |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
|
Item type |
E-Book |