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Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip

by Onabajo, Marvin.
Authors: Silva-Martinez, Jose.%author. | SpringerLink (Online service) Physical details: XI, 187p. 125 illus. online resource. ISBN: 1461422965 Subject(s): Engineering. | Computer science. | Electronics. | Systems engineering. | Engineering. | Circuits and Systems. | Electronics and Microelectronics, Instrumentation. | Processor Architectures.
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E-Book E-Book AUM Main Library 621.3815 (Browse Shelf) Not for loan

Introduction -- Process Variation Challenges and Solutions Approaches -- High-Linearity Transconductance Amplifiers with Digital Correction Capability -- Multi-Bit Quantizer Design for Continuous-Time Sigma-Delta Modulators with Reduced Device Matching Requirements -- An On-Chip Temperature Sensor for the Measurement of RF Power Dissipation and Thermal Gradients -- Mismatch Reduction for Transitiors in High-Frequency Differential Analog Signal Paths -- Summary and Conclusions.

This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements.    Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters; Includes built-in testing techniques, linked to current industrial trends; Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches; Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.

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