Scalable and Ultra-Low-Power Digital Integrated Circuits -- Subthreshold Source-Coupled Logic -- STSCL Standard Cell Library Development -- Subthreshold Source-Coupled Logic Performance Analysis -- Low-Activity-Rate and Memory Circuits in STSCL -- Subthreshold MOS for Ultra-Low Power -- Scalable and Ultra-Low-Power Analog Integrated Circuits -- Widely Adjustable Continuous-Time Filter Design -- Scalable Folding and Interpolating ADC Design -- Widely Adjustable Ring Oscillator Based ?? ADC -- Wide Tuning Range PLL -- Conclusions.

This book describes a completely novel class of techniques for designing ultra-low-power integrated circuits (ICs). In many applications such as battery operated systems and battery-less (energy-scavenging) systems, power dissipation is a critical parameter. As a result, there is a growing demand for reducing the power (energy) consumption in ICs to extremely low levels, not achievable by using classical "subthreshold CMOS" techniques. This book introduces a new family of "subthreshold circuits" called "source-coupled circuits". This family of circuits can be used for implementing digital (logic) circuits that dissipate far less than 1fJ per switching event, yet maintain the noise margins that are necessary for robust operation. This book also explains how the techniques used for implementing ultra low-power digital circuits could be extended for implementing analog circuits. Developing a uniform basis for designing ultra-low-power digital and analog circuits provides the basis for realizing complicated mixed-signal integrated systems.