Introduction -- Related Work -- Background -- Architectural Selection using High Level Synthesis -- Statistical Regression Based Power Models -- Coprocessor Design Space Exploration Using High Level Synthesis -- Regression-based Dynamic Power Estimation for FPGAs -- High Level Simulation Directed RTL Power Estimation -- Applying Verification Collaterals for Accurate Power Estimation -- Power Reduction using High-Level Clock-gating -- Model-Checking to exploit Sequential Clock-gating -- System Level Simulation Guided Approach for Clock-gating -- Conclusions.

Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process. This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design; Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives; Covers techniques from RTL/gate-level to hardware software co-design.