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Electromigration Modeling at Circuit Layout Level

by Tan, Cher Ming.
Authors: He, Feifei.%author. | SpringerLink (Online service) Series: SpringerBriefs in Applied Sciences and Technology, 2191-530X Physical details: IX, 103 p. 75 illus., 2 illus. in color. online resource. ISBN: 9814451215 Subject(s): Engineering. | System safety. | Engineering. | Quality Control, Reliability, Safety and Risk. | Electronic Circuits and Devices. | Atomic, Molecular, Optical and Plasma Physics.
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E-Book E-Book AUM Main Library 658.56 (Browse Shelf) Not for loan

Introduction -- 3D Circuit Model Construction and Simulation -- Comparison of EM Performance in Circuit Structure and Test Structure -- Interconnect EM Reliability Modeling at Circuit Layout Level -- Conclusion.

Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels.  Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level. 

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